Anlage Infotech India Private Limited
Bangalore, IN · On-site · Full-time
Design Verification Design Lead – PCIe / SystemVerilog / UVM
Posted 1 month ago
- Location
- Bangalore, IN
- Work mode
- On-site
- Employment
- Full-time
- Experience
- Lead
About the role
We are looking for an experienced Design Verification (DV) Design Lead with strong expertise in PCIe SystemC IP / Subsystem Verification to drive high-quality pre-silicon verification and ensure robust, bug-free silicon. The ideal candidate will have strong hands-on experience in SystemVerilog, UVM, functional and formal verification , verification planning, coverage closure, regression automation, and verification sign-off. Experience with mixed-signal IP, RNM/Verilog-A, C/MATLAB modelling, Sp…