Impactful ISP RTL Design Engineer at ovt | Rozgoo | Rozgoo

ovt

Singapore, SG · On-site · Full-time

Impactful ISP RTL Design Engineer

₹51K – ₹83KPosted 12 days ago

Location: Singapore, SG
Work mode: On-site
Employment: Full-time
Salary: ₹51K – ₹83K
Experience: Mid-level · 4+ yrs
Education: bachelor's

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About the role

ovt is seeking an experienced Digital Design engineer to implement ISP algorithms into hardware using Verilog, SystemVerilog, and SystemC. You will define architectures with performance and power targets, verify at multiple levels, and optimize gate count and power consumption. Collaboration with the ISP Algorithm Team is essential. The role requires a strong background in CMOS image sensors, ISP concepts, and toolchains including SystemC/C++, SystemVerilog, and Catapult HLS. J-18808-Ljbffr

Requirements

experience with Verilog, SystemVerilog, and SystemC
knowledge of CMOS image sensors and ISP concepts
bs degree in relevant field
experience in digital hardware design
experience in hardware verification
familiarity with SystemC/C++ and Catapult HLS

Skills

verilog
systemverilog
systemc
systemc/c++
catapult hls
cmos image sensors
isp algorithms
hardware verification
power optimization
architecture definition
gate count optimization

About the company

ovt

Posted via Adzuna

How to apply

Apply Now takes you to Rozgoo, where auto-apply can submit your application for this role. Updated 9 days ago.

ovt

Impactful ISP RTL Design Engineer

₹51K – ₹83K