Memory Layout Lead at ACL Digital | Rozgoo | Rozgoo

ACL Digital

Bangalore, IN · On-site · Full-time

Memory Layout Lead

Posted 24 days ago

Location: Bangalore, IN
Work mode: On-site
Employment: Full-time
Experience: Lead · 7+ yrs
Education: bachelor's

About the role

© 2026 Rozgoo

Memory Layout Engineer | ACL Digital Location: Bangalore ⏳ Experience: 7 Years ⏱️ Notice Period: 0–30 Days We are hiring an experienced Memory Layout Engineer to design and optimize high-density memory architectures (SRAM/DRAM/HBM/Flash) on advanced sub-5nm process nodes (FinFET/GAAFET). In this role, you will lead custom block floorplanning, execute matched differential routing for word/bit lines, and ensure zero-error physical verification (DRC, LVS, ERC). You will collaborate closely with c…

Requirements

7+ years experience in memory layout engineering
Knowledge of sub-5nm semiconductor processes
Experience with FinFET and GAAFET technologies
Proficient in physical verification tools and methods
Bachelor's degree in relevant engineering field
Strong floorplanning and routing skills

Skills

memory layout
sram
dram
hbm
flash memory
sub-5nm process
finfet
gaafet
floorplanning
routing
physical verification
drc
lvs
erc

About the company

ACL Digital

Posted via Adzuna

How to apply

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ACL Digital

Memory Layout Lead