- Location
- India, IN
- Work mode
- On-site
- Employment
- Full-time
- Experience
- Mid-level · 5–8 yrs
About the role
Position: RTL2PD_ Analog Design Engineer Job Description: JD 5 to 8 years of experience in RTL Synthesis, Timing Constraints / SDC checking / reviewing / small fixes / finding errors etc. Should have done at least 3 ASIC projects. CDC, Lint clean up and automation with scripts. Timing Report analysis, Static Timing Analysis Tools : Genus / FC : Synthesis, Optimization or DC compiler, DCTopo Spyglass : Constraints checking / CDC Checking LEC / Formality : Formal Verification, VCLP. Primetime : Z…