- Location
- India, IN
- Work mode
- On-site
- Employment
- Full-time
- Experience
- Lead · 4–5 yrs
About the role
Senior DFT Engineer Experience : 4–5 years Location : Bangalore Experience to join our Silicon Engineering team. In this role, you will lead end-to-end DFT strategies—including Scan compression, MBIST, IJTAG, and ATPG pattern generation—for high-performance, sub-10nm SoCs. Candidates must have expertise in top-tier EDA tools (Tessent, Synopsys, or Cadence) and a notice period of 0–30 days . Ready to elevate your career? Send your resume to janagaradha.n@acldigital.com today!
Requirements
- 4 to 5 years experience in DFT
- Experience with scan compression, MBIST, IJTAG
- Proficiency with EDA tools like Tessent, Synopsys, Cadence
- Knowledge of ATPG pattern generation
- Experience in sub-10nm SoCs testing
- Ability to join within 30 days
Skills
- dft
- scan compression
- mbist
- ijtag
- atpg pattern generation
- eda tools
- tessent
- synopsys
About the company
ACL Digital
Posted via Adzuna
How to apply
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