- Location
- Hyderabad, IN
- Work mode
- On-site
- Employment
- Full-time
- Experience
- Lead
About the role
Key Responsibilities Own and execute hierarchical scan insertion and ATPG flows for SoCs/MCUs Integrate and verify MBIST at RTL level across various memory instances Enable LBIST integration, RTL and gate-level coverage analysis, and GLS (Gate-Level Simulation) Implement and verify IEEE1149.1 (JTAG) and IJTAG standards for boundary scan and internal test Conduct post-silicon debug of DFT patterns and drive root-cause analysis Collaborate daily with RTL design, physical design, and verification …
Skills
- dft
- atpg
- scan insertion
- mbist
- lbist
- rtl coverage
- gate-level simulation
- jtag
- ieee 1149.1
About the company
Renesas
Posted via Adzuna
How to apply
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