STA Engineer

Lead block-level and full-chip STA signoff for HBM products across all PVT corners. Own development and validation of SDC constraints , including clocks, generated clocks, false paths, multicycle paths, case analysis, and async constraints. Drive timing closure by analyzing and resolving setup/hold, recovery/removal, slew, fanout, and clock-related violations. Implement clocking solutions for complex HBM designs, including generated clocks, pulse clocks, and zero-cycle, single-cycle, and multi-…