- Location
- Hyderabad, IN
- Work mode
- On-site
- Employment
- Full-time
- Experience
- Fresher · 8–13 yrs
About the role
Responsibilities Manage hierarchical scan insertion and ATPG flow Integrate and verify MBIST at the RTL level Handle RTL integration, verification, gate-level coverage, and GLS enablement for LBIST Implement and verify IEEE1149.1 JTAG and IJTAG standards Lead post-silicon debug activities related to DFT patterns Collaborate daily with RTL design, physical design, and verification teams Mentor and guide junior engineers in DFT methodologies Skills: MBIST, Scan Insertion Experience: 8.00-13.00 Ye…