Static Timing Analysis Engineer

• Experience with static timing analysis
• Knowledge of digital ASIC/SoC design
• Ability to interpret timing reports and violations

• static timing analysis
• timing closure
• constraints (sdc)
• asic
• digital design
• clock domain analysis
• primetime
• vivado
• synopsys
• cadence
• tcl

Apply Now takes you to Rozgoo, where auto-apply can submit your application for this role. Updated 4 days ago.